USB0 NAME:"\\?\usb#vid_0547&pid_1006#7&1f5985dd&0&2#{{dd763f66-1de4-453f-865d-b143cb25bb9f}}"
USB1 NAME:"\\?\usb#vid_0547&pid_1006#7&1f5985dd&0&4#{{dd763f66-1de4-453f-865d-b143cb25bb9f}}"
USB port 0 is set as sink
FPGA version: 2.10
    TE_configure
    pll_set
    configure
    tx_configure(HDMI)
    rx_configure(HDMI)
    sink::hdcp_disable
    TE_check
-- Clock Information =================================================
-- HDMI Sub : (Rx)27, (Tx)27
-- HDMI Side: (0)24, (1)UnLock, (2)UnLock, (3)UnLock
-- CLKA: 60MHz, 48MHz
-- CLKB: 49MHz, 168MHz
-- CLKC: 74MHz, 150MHz
-- Clock Information =================================================
--          [TE enable]      [HDMI]  [HDCP Ver]  [Trig buf]
-- HDMI Tx:     Disable     Connect          No        1352
-- HDMI Rx:      Enable     Connect          No          80
-- Rx DDC(3): 0x70 Polling interval(130.3125ms(62)), DDC Freq(Stop)
-- 0x0 Polling interval(0): 0ms
-- Tx DDC: 3
    init
System Timer:63764883199701ms
sink TE RTL Timer:0.375ms
    source rx_msg_buf_init
    sink rx_msg_buf_init
